Six-layer RK3399 carrier board

A carrier board for a Rockchip RK3399 system-on-module on an impedance-controlled stackup. PCIe to an SSD, two radios, three point-of-load rails.

Released Gessler GmbH 2025–2026 9 min read Confidential

Role

Layout and impedance control

Ownership

Contributed · a team board, not a solo one

Scope

Power section · two RF paths · PCIe pairs · SD card interface

Power tree

3.3 V · 5 V · 12 V point-of-load bucks

Standards

IPC-2221B

Stackup

Six layers · impedance targets defined before layout

Representative model. Not the client's design.

What it is

A six-layer carrier board for a Rockchip RK3399 system-on-module, on an impedance-controlled stackup. It carries a point-of-load power tree, a PCIe-attached SSD, an SD card interface, and two radios brought out to SMD SMA connectors — one LTE, one Bluetooth Low Energy.

I placed and routed the power section, the two RF paths, the PCIe differential pairs to the SSD, and the SD card interface, then worked the schematic and component review comments through to release and contributed to the documentation package.

This was a team board. The stackup and the impedance targets were defined before layout started; I worked inside them rather than setting them.

Decisions

Kind

Design decision
Problem found
Verification

Design decision U4 · PCIe

Differential pairs to the SSD

Found: First differential pairs routed to a real target.
Did: Kept each pair on a single layer over a continuous reference plane; held intra-pair skew tight by matching within the pair before matching pair to pair; kept the pairs away from the switching nodes of the buck converters; stitched ground around the transitions.
Result: Length matching done against the budget the stackup gave me rather than a number I invented.

Design decision U4 · RF

Two radios on one board

Found: LTE and BLE both terminate at SMD SMA connectors. The work is in the launch and the isolation.
Did: A clean transition from the coplanar feed into the connector; ground vias tight around the launch so the return path does not have to travel; enough separation and ground between the two paths that the LTE transmit path is not sitting on top of the BLE receive path.

Design decision U4 · floorplan

Switching converters next to sensitive nets

Found: A carrier board puts three buck converters a few centimetres from RF and PCIe.
Did: Kept each converter's high di/dt loop small and local, gave each one its own return area, planned the floorplan so the noisy corners and the sensitive corners are not the same corner.
Result: The same discipline as the mains work, at a different frequency.

Verification

What I would not claim

I did not define the stackup or the impedance targets, and I have not run signal integrity simulation on this board. What I have done is route to a defined impedance target, length match a differential interface, and lay out RF connector launches on a board that went to fabrication.

That is a smaller claim than owning the high-speed design, and it is the true one.

What is not shown here, and why

The schematic, the layout and the stackup definition are Gessler GmbH intellectual property. The reasoning and the decisions above are mine.

What I cannot do is hand over the designs themselves, and I would not want to work somewhere that wanted me to.

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